Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance. Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
As transistor pitch scales down to 64 nanometers (nm) and below, borderless, or self-aligned (SAC), contacts are essentially required to avoid massive gate to source/drain contact shorts, to reduce source/drain resistance by enabling an increase in the width of contact plugs, and to increase the lithography/etching process window for stringent critical dimension and T2T requirements. An SAC contact compatible flow is critically important for 14 nm technologies and below. Formation of a dielectric cap layer on top of the replacement metal gate (RMG) structure is a key process to enable the SAC contact for the gate last CMOS flow.
Prior attempts to form a dielectric cap layer for an RMG gate structure entail oxidizing, nitridizing, or fluorinating the top metal surface. However, those attempts necessitate a single type of metal for the top metal layer, while the top metal composition actually is complex. Further, for subsequent processes, a cap layer having a thickness of at least 15 nm is required, which is impractical with conventional oxidation, nitridation, and fluorination processes, particularly for 14 nm CMOS transistors. In addition, for high-k/metal gate stacks, there are stringent temperature and oxygen control requirements after the RMG is formed, which conflict with direct oxidation, nitridation, and fluorination processes.
A need therefore exists for methodology enabling formation of a thick dielectric cap layer for an RMG structure with no thermal budget or oxygen concerns, and the resulting structure.